P1727 notebook lcd panel emi reduction ic ?2010 scillc. all rights reserved. publication order number: january 2010 C rev. 1 P1727/d features fcc approved method of emi attenuation generates a low emi spread spectrum of the input clock frequency optimized for frequency range: P1727x: 20mhz to 40mhz internal loop filter minimizes external components and board space 8 different frequency deviations ranging from 0.625% to C3.50% low inherent cycle-to-cycle jitter 3.3v operating voltage supports notebook vga and other lcd timing controller applications available in 8-pin soic. product description the P1727 is a versatile spread spectrum frequency modulator designed specifically for a wide range of clock frequencies. the P1727 reduces electromagneti c interference (emi) at the clock source, allowing sy stem wide reduction of emi of down stream (clock and dat a dependent signals). the P1727 allows significant system cost savings by reducing the number of circu it board layers and shielding that are traditionally r equired to pass emi regulations. the P1727 modulates the output of a single pll in order to spread the bandwidth of a synthesized cl ock, thereby decreasing the peak amplitudes of its harmonics. this result in significantly lower syste m emi compared to the typical narrow band signal produced by oscillators and most clock generators. lowering emi by increasing a signals bandwidth is called spread spectrum clock generation. the P1727 uses the most efficient and optimized modulation profile approved by the fcc and is implemented by using a proprietary all-digital meth od. applications the P1727 is targeted towards notebook lcd displays , other displays using an lvds interface, pc peripher al devices and embedded systems. block diagram clkin vss loop filter modulation vdd frequency divider feedback divider phase detector vco pll pdb output divider refout modout
P1727 rev. 1 | page 2 of 6 | www.onsemi.com pin configuration table 1 C power down selection pdb spread spectrum modout pll mode 0 n/a disabled disabled power down 1 on normal normal normal table 2 C frequency deviation selection p/ n deviation p/n deviation P1727a -1.25% P1727e 0.625% P1727b -1.75% P1727f 0.875% P1727c -2.50% P1727g 1.25% P1727d -3.50% P1727h 1.75% pin description pin# pin name type description 1 clkin i external reference frequency input. connect to exte rnally generated reference signal. 2 vdd p connect to +3.3v. 3 vss p ground connection. connect to system ground . 4 modout o spread spectrum clock output. 5 refout o reference output. 6 nc no connect. 7 nc no connect. 8 pdb i powerdown pin. pull low to disable spread s pectrum clock output. nc refout 1 2 3 4 5 6 7 8 P1727 vdd vss modout nc pdb clkin
P1727 rev. 1 | page 3 of 6 | www.onsemi.com schematic for notebook vga application absolute maximum ratings symbol parameter rating unit vdd, v in voltage on any pin with respect to ground -0.5 to +7 v t stg storage temperature -65 to +125 c t s max. soldering temperature (10 sec) 260 c t j junction temperature 150 c t dv static discharge voltage (as per jedec std22- a114 -b) 2 kv note: these are stress ratings only and are not imp lied for functional use. exposure to absolute maxim um ratings for prolonged periods of time may affect device reliability. operating conditions symbol parameter min max unit vdd supply voltage with respect to vss 3.0 3.6 v t a operating temperature -40 +85 c c l load capacitance 15 pf c in input capacitance 7 pf vdd P1727 clkin vdd nc refout vss modout nc 1 2 3 4 5 6 7 8 pdb 0.1 f tie low to enable powerdown mode. 27mhz pixel clock input modout clock reference c lock o/p clkin
P1727 rev. 1 | page 4 of 6 | www.onsemi.com dc electrical characteristics symbol parameter min typ max unit v il input low voltage vss C 0.3 0.8 v v ih input high voltage 2.0 vdd +0.3 v i il input low current -35 a i ih input high current 35 a v ol output low current vdd = 3.3v, i ol = 20ma 0.4 v v oh output high current vdd = 3.3v, i oh = 20ma 2.5 v i dd static supply current (clkin, pdb pulled low) 2 ma i cc dynamic supply current (no load) 14 18 ma v dd operating voltage 3.0 3.3 3.6 v t on power up time (first locked clock cycle after powe r up) 0.18 ms z out clock output impedance 50 ac electrical characteristics symbol parameter min typ max unit f in input frequency: P1727x 20 40 mhz f out output frequency: P1727x 20 40 mhz t lh 1 output rise time measured from 0.8v to 2.0v 0.7 0 .9 1.1 ns t hl 1 output fall time measured from 2.0v to 0.8v 0.6 0 .8 1.0 ns t jc jitter (cycle-to-cycle) 225 325 ps t d output duty cycle 45 50 55 % note: 1. t lh and t hl are measured with a capacitive load of 15pf.
P1727 rev. 1 | page 5 of 6 | www.onsemi.com package information 8-lead (150-mil) soic package d e h d a1 a2 a q l c b e symbol dimensions inches millimeters min max min max a1 0.004 0.010 0.10 0.25 a 0.053 0.069 1.35 1.75 a2 0.049 0.059 1.25 1.50 b 0.012 0.020 0.31 0.51 c 0.007 0.010 0.18 0.25 d 0.193 bsc 4.90 bsc e 0.154 bsc 3.91 bsc e 0.050 bsc 1.27 bsc h 0.236 bsc 6.00 bsc l 0.016 0.050 0.41 1.27 0 8 0 8
P1727 note: this product utilizes us patent #6,646,463 im pedance emulator patent issued to pulsecore semicon ductor, dated 11-11-2003. on semiconductor and are registered trademarks of semiconductor componen ts industries, llc (scillc). scillc reserves the ri ght to make changes without further notice to any products herein. sci llc makes no warranty, representation or guarantee regarding the suitability of its products for any p articular purpose, nor does scillc assume any liability arisi ng out of the application or use of any product or circuit, and specifically disclaims any and all lia bility, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applica tions and actual performance may vary over time. al l operating parameters, including typicals must b e validated for each customer application by customer 's technical experts. scillc does not convey any l icense under its patent rights nor the rights of ot hers. scillc products are not designed, intended, or auth orized for use as components in systems intended fo r surgical implant into the body, or other applicat ions intended to support or sustain life, or for any oth er application in which the failure of the scillc p roduct could create a situation where personal inju ry or death may occur. should buyer purchase or use scillc pro ducts for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs , damages, and expenses, and reasonable attorney fe es arising out of, directly or indirectly, any claim of person al injury or death associated with such unintended or unauthorized use, even if such claim alleges tha t scillc was negligent regarding the design or manufacture o f the part. scillc is an equal opportunity/affirmat ive action employer. u.s patent pending; timing-sa fe and active bead are trademarks of pulsecore semicon ductor, a wholly owned subsidiary of on semiconduct or. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone: 303-675-2175 or 800-344-3860 toll free usa/canada fax: 303-675-2176 or 800-344-3867 toll free usa/canada email: orderlit@onsemi.com n. american technical support: 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature: http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ordering information part number marking package configuration temperature range P1727af-08sr abw 8-pin soic, tape & reel, green 0c to +70c a microdot placed at the end of last row of marki ng or just below the last row toward the center of package indicates pb-free. licensed under us patent #5,488,627, #6,646,463 and #5,631,920.
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